Prior art TTL compatible input circuits for CMOS devices are typified by the circuit of FIG. 1. Devices Q.sub.1 (a P-type MOSFET) and Q.sub.2 (an N-type) must be ratioed for a specific supply voltage, V.sub.cc ; that is, the ratio of the width to length of the gate of transistor Q.sub.1 with respect to the same ratio of transistor Q.sub.2 must be adjusted to attain the desired result for any particular supply voltage.
With a minimal high logic level TTL input voltage (V.sub.IH) at input node 10 equal to 2.1 volts (which must be assumed for the purpose of reliable design), Q.sub.1 is always conducting (independent of whether Q.sub.2 is in an "on" or "off" state) and for a supply of 12 volts, the supply current drain is about 60 uA (or higher, depending upon the speed requirements of the circuit) with Q.sub.2 "on." For Q.sub.2 to sink the current from Q.sub.1 and drive the output to ground with V.sub.IN =2.1 volts, Q.sub.2 must be very large.
The prior art circuit of FIG. 1 is subject to problems due to supply line voltage shifts (since the required ratio of gate sizes is dependent upon that voltage), requires relatively high DC current supply drain and has a relatively long propagation delay time, in addition to the aforementioned large area requirement of transistor Q.sub.2.
U.S. Pat. No. 4,350,710, by Cohen et al., discloses a TTL to CMOS interface circuit which utilizes a FET inverter with its N channel being a part of a first current mirror and its P channel being part of a second current mirror. The inverter output is the reference signal input to the current mirrors. The current sources for each control leg of the two current mirror circuits are variable; in the first case to compensate for variations in the input signal, in the second case to compensate the inverter for manufacturing tolerances.
U.S. Pat. No. 4,472,647, by Allgood et al., also employs current mirror circuits in a design which accepts either CMOS or TTL level input signals. Neither of these patents discloses a circuit such as the one described, infra.